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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. mos integrated circuit pd720133 usb2.0 to ide bridge document no. s17100ej2v0ds00 (2nd edition) date published june 2004 ns cp (n) printed in japan preliminary data sheet 2004 the mark shows major revised points. the pd720133 is designed to function as a bridge between usb 2.0 and ata/atapi. the pd720133 complies with the universal serial bu s specification revision 2.0 full-/high-speed signaling and works up to 480 mbps. the pd720133 consists of a cisc processor, an ata/atapi controller, an endpoint co ntroller (epc), a serial interface engine (sie), and an usb2.0 transceiver. the usb2.0 protocol and class specific protocol s (bulk only protocol) are handled by the usb2.0 transceiver, the sie a nd the epc. the v30mz cisc processor in the pd720133 takes care of the activities in the transport laye r. the firmware controlling the pd720133 is located in an embedded rom. features ? compliant with universal serial bus specif ication revision 2.0 (data rate 12/480 mbps) ? compliant with ata/atapi-6 (lba48, pio mode 0-4, multi word dma mode 0-2, ultra dma mode 0-4) ? usb2.0 high-speed bus powered device capability ? certified by usb implementers forum and grant ed with usb 2.0 high-speed logo (tid: 40001985) ? one usb2.0 high-speed transceiver / receiver with full-speed transceiver / receiver ? usb2.0 high-speed or full-speed packet protocol sequencer (serial interface engine) ? automatic chirp assertion and full-/high-speed mode change ? usb reset, suspend and resume signaling detection ? supports power control functionality for ide device as cd-rom and hdd ? supports set feature (test_mode) functionality ? system clock is generated by 30 mhz x?tal ? 2.5 v and 3.3 v power supply ordering information part number package pd720133gb-yeu-a 64-pin plastic tqfp (fine pitch) (10 10) lead-free product pd720133gb-yeu-y 64-pin plastic tqfp (fine pitch) (10 10) high heat-resistance product
preliminary data sheet s17100ej2v0ds 2 pd720133 block diagram cpu core (v30mz) bus bridge ram 2 kbytes x 2 rom 12 kbytes dmac intc direct bus 16-bit bus 16-bit bus pio timer idec_v2 epc2_v2 dcc phy_v2 gpio direct command bus ide bus serial rom 8-bit bus usb bus gpio v30mz : cisc cpu core ram : 4-kbyte work ram for firmware rom : 12-kbyte rom for built-in firmware phy_v2 : usb2.0 transceiver with serial interface engine epc2_v2 : endpoint controller idec_v2 : ide controller dcc : ata direct command controller bus bridge : internal / external bus controller and dma controller intc : interrupt controller (82c59 like) gpio : general purpose 3-bit i/o controller pio : multipurpose 2-bit i/o controller
preliminary data sheet s17100ej2v0ds 3 pd720133 pin configuration (top view) ? 64-pin plastic tqfp (fine pitch) (10 10) pd720133gb-yeu-a pd720133gb-yeu-y 1 8 16 17 25 32 48 41 33 64 56 49 scan rpu v dd25 v ss rsdp dp v dd33 dm rsdm v ss av dd25 av ss rref av ss (r) av dd25 test vbus idecs1b idecs0b idea2 idea0 idea1 ideint v dd33 v ss v dd25 idedakb ideiordy ideiorb ideiowb idedrq v ss ide9 ided5 ided10 ided4 ided11 ided3 ided12 v dd33 v ss v dd25 ided2 ided13 ided1 ided14 ided0 ided15 cmb_bsy cmb_state dpc scl sda resetb v dd25 v ss xout xin v dd33 iderstb ided7 ided8 ided6 v ss
preliminary data sheet s17100ej2v0ds 4 pd720133 pin no pin name pin no pin name pin no pin name pin no pin name 1 scan 17 vbus 33 ided15 49 v ss 2 rpu 18 idecs1b 34 ided0 50 ided6 3 v dd25 19 idecs0b 35 ided14 51 ided8 4 v ss 20 idea2 36 ided1 52 ided7 5 rsdp 21 idea0 37 ided13 53 iderstb 6 dp 22 idea1 38 ided2 54 v dd33 7 v dd33 23 ideint 39 v dd25 55 xin 8 dm 24 v dd33 40 v ss 56 xout 9 rsdm 25 v ss 41 v dd33 57 v ss 10 v ss 26 v dd25 42 ided12 58 v dd25 11 av dd25 27 idedakb 43 ided3 59 resetb 12 av ss 28 ideiordy 44 ided11 60 sda (pio0) 13 rref 29 ideiorb 45 ided4 61 scl (pio1) 14 av ss (r) 30 ideiowb 46 ided10 62 dpc(gpio5) 15 av dd25 31 idedrq 47 ided5 63 cmb_state(gpio6) 16 test 32 v ss 48 ided9 64 cmb_bsy(gpio7) remark av ss (r) should be used to connect rref through 1 % precision reference resistor of 2.43 k ? .
preliminary data sheet s17100ej2v0ds 5 pd720133 1. pin information pin name i/o buffer type active level function xin i 2.5 v input system clock input or oscillator in xout o 2.5 v output oscillator out resetb i 3.3 v schmitt input low asynchronous reset signaling idecs(1:0)b o (i/o) 5 v tolerant output low ide host chip select idea(2:0) o (i/o) 5 v tolerant output ide address bus ideint i 5 v tolerant input high ide interrupt request from device to host idedakb o (i/o) 5 v tolerant output low ide dma acknowledge ideiordy i 5 v tolerant input high ide io channel ready ideiorb o (i/o) 5 v tolerant output low ide io read strobe ideiowb o (i/o) 5 v tolerant output low ide io write strobe idedrq i 5 v tolerant input high ide dma request from device to host ided(15:0) i/o 5 v tolerant i/o ide data bus iderstb o (i/o) 5 v tolerant output low ide reset from host to device cmb_bsy (gpio7) i/o 3.3 v i/o combo ide bus busy cmb_state (gpio6) i/o 3.3 v i/o combo ide bus state dpc (gpio5) i/o 3.3 v i/o power control signaling for ide device sda (pio0) i/o 3.3 v i/o serial rom data signaling scl (pio1) i/o 3.3 v i/o serial rom clock signaling vbus i 5 v schmitt input note vbus monitoring dp i/o usb high speed d+ i/o usb?s high speed d+ signal dm i/o usb high speed d ? i/o usb?s high speed d ? signal rsdp o usb full speed d+ output usb?s full speed d+ signal rsdm o usb full speed d ? output usb?s full speed d ? signal rpu a usb pull-up control usb?s 1.5 k ? pull-up resistor control rref a analog reference resistor scan i 3.3 v input scan mode control test i 3.3 v input test mode setting av dd25 2.5 v v dd for analog circuit v dd25 2.5 v v dd v dd33 3.3 v v dd av ss v ss for analog circuit v ss v ss note vbus pin may be used to monitor for vbus line even if v dd33 , v dd25 , and av dd25 are shut off. the system designer must ensure that the input voltage level fo r vbus pin is less than 3.0 v. [that is the absolute maximum rating]. remarks 1. ?5 v tolerant? means that the buffer is a 3.3 v buffer with 5 v tolerant circuit. 2. the signal marked as ?(i/o)? in t he above table operates as i/o signals during testing. they should be ignored under normal operation.
preliminary data sheet s17100ej2v0ds 6 pd720133 2. function information the usb to ide system can be realized by pd720133. if the customizations of data such as usb vendor id and usb product id are required, an external serial rom can be used. the pd720133 also has power circuit to turn on and off the system power supply. the pd720133 can operate in either bus-powered mode or self-powered mode. if the total power consumption of the usb to ide system within the usb 2.0 specification of a bus powered device, it will be possible to realize a high-speed capable bus powered system. in addition, pd720133 has a feature of ide bus arbitration. this enables system, which has two ide controller s to control a single ide device. in this case, another ide controller also must have a fe ature of ide bus arbitration. the setting of ide controller in the pd720133 is controlled by data in serial rom. 2.1 data in serial rom the pd720133 loads some data such as vendor id, produ ct id and some additional usb related information, etc from serial rom during pd720133 initialization. table 2-1. data in serial rom offset (h) data size symbol description +00 1 word idmark validation mark of 55aah +02 1 word checksum check sum of serial rom +04 1 word flags control for descriptor overwrite +06 1 byte modereset pwr, clc, d cc, dv[1:0], dpc reset bit map field +07 1 byte modeset pwr, clc, dcc, dv[1:0], dpc set bit map field +08 1 word idvendor idvendor field in device descriptor +0a 1 word idproduct idproduct field in device descriptor +0c 1 word bcddevice bcddevic e field in device descriptor +0e 1 word reserved reserved for future use. +10 1 byte maxpower bus bmaxpower field in configuration descriptor for bus powered mode +11 1 byte maxpower self bmaxpower field in configuration descriptor for self powered mode +12 1 byte binterfaceclass binterface class field in interface descriptor +13 1 byte binterfacesubclass binterfacesubclass field in interface descriptor +14 1 byte binterfaceprotocol binterface protocol field in interface descriptor +15 1 byte reserved reserved for future use. +16 1word txmodereset ide transmission type su ch as ultra dma 66 reset bit map field +18 1word txmodeset ide transmission type su ch as ultra dma 66 set bit map field +1a 1word rompatchsw rom patch information (patch on or off) of external function +1c 4 bytes reserved reserved for future use. +20 32 bytes manufacturestring string descriptor for manufacturer +40 32 bytes productstring string descriptor for product +60 32 bytes serialstring string descr iptor for device serial number +80 128 n bytes fw patch firmware patch module for self-powered/bus-powered mode
preliminary data sheet s17100ej2v0ds 7 pd720133 2.2 pin setting settings of the scl, sda and unused pins (test and scan ) are recommended as follows. please note that the setting of the scl depends on size of serial rom. table 2-2. pin settings pin name setting scl pull up note sda pull up test low clamp scan low clamp note if serial rom size is more than 2 kbytes, scl should be pull down. the settings for any other pins such as the cmb_ bsy and the cmb_state depend on usb2.0 to ide bridge system. for example, if two ide cont rollers are implemented in the system to control one target ide device and one of the two ide controllers is the pd720133, then both the cmb_bsy and t he cmb_state are used to handshake between the two ide controller chips. on the other hand, when th e system uses the pd720133 as the only ide controller to control a target id e device, then both the cmb_bsy and t he cmb_state should be connected to ground.
preliminary data sheet s17100ej2v0ds 8 pd720133 2.3 control bit in serial rom the following tables show ide status and control bit in serial rom. table 2-3. dv1/dv0, clc, pwr setting no. device power internal clock ata/atapi pwr clc dv1 dv0 0 no device connected 1 1 1 1 1 ata 1 1 1 0 2 atapi 1 1 0 1 3 7.5 mhz reserved 1 1 0 0 4 no device connected 1 0 1 1 5 ata 1 0 1 0 6 atapi 1 0 0 1 7 bus powered 60 mhz reserved 1 0 0 0 8 no device connected 0 1 1 1 9 combo (ata) 0 1 1 0 10 combo (atapi) 0 1 0 1 11 combo auto device detect 0 1 0 0 12 no device connected 0 0 1 1 13 ata 0 0 1 0 14 atapi 0 0 0 1 15 self powered 60 mhz auto device detect 0 0 0 0 remarks 1. setting of no. 0, 3, 4, 7, 8, and 12 are not allowed. 2. for bus powered setting, some critical consideratio ns such as power consumption for the total system should be observed. 3. the slave device function cannot use auto device detect. table 2-4. dv1/dv0, dcc setting condition dv1 dv0 mode target device dcc setting in serial rom description reset ultra, multi word dma are disabled. 1 0 ata ata set ultra, multi word dma are enabled. reset ultra dma are disabled. 0 1 atapi atapi set ultra, multi word dma are enabled. reset ultra, multi word dma are disabled. ata set ultra, multi word dma are enabled. reset ultra dma are disabled. 0 0 auto device detect atapi set ultra, multi word dma are enabled. remark pio mode 0-4 are always enabled.
preliminary data sheet s17100ej2v0ds 9 pd720133 2.4 combo mode function the pd720133 can be used to realize that two ide controller chips control one target ide device in one system. in order to realize ide bus arbitrati on between two ide controller chips, the pd720133 has the cmb_bsy and the cmb_state. combo mode is enabled when pwr = 0 and clc = 1. cmb_bsy and cmb_state are connected to another ide controller chip as shown below. figure 2-1. cmb_bsy and cmb_state connection between two ide controller chips other ide controller ide bus request cmb_state cmb_bsy ide bus grant pd720133 table 2-5. description of cmb_bsy and cmb_state pin name direction value description 0 other ide controller does not require or does not use ide bus. cmb_state in 1 other ide controller requires or is using ide bus. 0 the pd720133 does not require or does not use ide bus. cmb_bsy out 1 the pd720133 requires or is using ide bus.
preliminary data sheet s17100ej2v0ds 10 pd720133 the ide bus arbitration will be performed in the following sequence. the pd720133 will check if the other ide controller is using the ide bus. if the other ide controller is not using the ide bus, the pd720133 will be able to use the ide bus. on the other hand, if t he other ide controller is using the ide bus, the pd720133 transmits to the suspend mode. and the pd720133 resumes on condition that the cmb_state becomes low level. after that, the arbitration will re start from the beginning of the sequence. figure 2-2. ide bus arbitration sequence the other ide controller is using ide bus. the other ide controller is still using ide bus. the other ide controller releases ide bus. start cmb_bsy = 1 cmb_state = 1 ? cmb_state = 0 ? cmb_bsy = 0 yes no no yes pwr = 0 & clc = 1 ? no yes end end a a a suspend mode cmb_state = 1 ? resume yes no b b chip init the pd720133 uses ide bus. the pd720133 cannot use ide bus.
preliminary data sheet s17100ej2v0ds 11 pd720133 2.5 power control to realize bus-powered or high performance self -powered usb2.0 to ide bridge system, the pd720133 has two internal system clock mode. one is 7.5 mhz fo r bus-powered mode and another is 60 mhz for self-powered mode. the pd720133 controls the power state by events as follows. the word with under line indicates event. the italic word indicates the power state. figure 2-3. power state control (a) bus-powered mode idle mode vbus off vbus on connect set configuration resume resume suspend hardware reset bus reset power off set configuration resume resume suspend suspend fs connect hs connect power = p enum_fs power = p enum_hs suspend suspend resume suspend resume power = p fs_b power = p hs_b power = p spnd power = p spnd power = p reset hs enumeration state suspend mode hs operation state fs operation state configured state fs enumeration state suspend mode configured state power off default state (b) self-powered mode power = p spnd power on vbus off vbus on connect set configuration resume resume suspend hardware reset bus reset power off set configuration resume resume suspend suspend fs connect hs connect power = p enum_fs power = p enum_hs power = p combo suspend suspend resume suspend resume power = p fs_s power = p hs_s power = p spnd power = p reset cmb_state = 0 cmb_state = 1 power off ide bus release state idle mode default state suspend mode hs operation state disconnect mode fs operation state configured state fs enumeration state suspend mode hs enumeration state configured state
preliminary data sheet s17100ej2v0ds 12 pd720133 to realize bus-powered usb2.0 to ide bridge system, pd720133 has a dpc pin to control the on and off of the ide device?s power supply according to the usb device states. dpc should be pull-up to 3.3 v because dpc output becomes high impedance state until the pd720133 is initialized. figure 2-4. dpc pin to control ide device?s power circuit dpc power on hardware reset bus reset set configuration un-configured default configured suspend occured resume occured suspend configured normal operation normal operation high impedance state the following example is a circuit for controlling the power supplies to ide device while the pd720133 is under default and un-configured state. also, the power supply to ide de vice is disabled during suspend state. power consumption of total system under default, un-co nfigured, and suspend state can be reduced by dpc pin. figure 2-5. power control circuit example pd720133 p-channel switch on pull-up 3.3v in out power supply rail ide device power dpc regulator
preliminary data sheet s17100ej2v0ds 13 pd720133 3. electrical specifications 3.1 buffer list ? 2.5 v oscillator interface xin, xout ? 3.3 v input buffer test, scan ? 3.3 v schmitt input buffer resetb ? 3.3 v i ol = 3 ma bi-directional buffer with input enable (or-type) sda, scl, dpc (gpio5), cmb_ state (gpio6), cmb_bsy (gpio7) ? 5 v schmitt input buffer vbus ? 5 v i ol = 6 ma bi-directional buffer with input enable (or-type) ided(15:0), ideint, ideiordy, idedrq, idecs(1: 0)b, idea(2:0), idedakb, ideiorb, ideiowb, iderstb ? usb interface dp, dm, rsdp, rsdm, rref, rpu remark ?5 v? refers to a 3.3 v buffer with 5-v tolerant circui t. therefore, it is possible to have a 5-v connection for an external bus, but the output level will be only up to 3.3 v, which is the v dd33 voltage.
preliminary data sheet s17100ej2v0ds 14 pd720133 3.2 terminology terms used in absolute maximum ratings parameter symbol meaning power supply voltage v dd33 , v dd25 indicates voltage range within which damage or reduced reliability will not result when power is applied to a v dd pin. input voltage v i indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin. output voltage v o indicates voltage range within which damage or reduced reliability will not result when power is applied to an output pin. output current i o indicates absolute tolerance value for dc current to prevent damage or reduced reliability when a current flows out of or into an output pin. operating temperature t a indicates the ambient temperature range for normal logic operations. storage temperature t stg indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current are applied to the device. terms used in recommended operating range parameter symbol meaning power supply voltage v dd33 , v dd25 indicates the voltage range for normal logic operations occur when v ss = 0 v. high-level input voltage v ih indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the high level states for normal operation of the input buffer. * if a voltage that is equal to or greater than the ?min.? value is applied, the input voltage is guaranteed as high level voltage. low-level input voltage v il indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the low level states for normal operation of the input buffer. * if a voltage that is equal to or lesser than the ?max.? value is applied, the input voltage is guaranteed as low level voltage. hysteresys voltage v h indicates the differential between the pos itive trigger voltage and the negative trigger voltage. input rise time t ri indicates allowable input rise time to input pins. input rise time is transition time from 0.1 v dd to 0.9 v dd . input fall time t fi indicates allowable input fall time to input pi ns. input fall time is transition time from 0.9 v dd to 0.1 v dd .
preliminary data sheet s17100ej2v0ds 15 pd720133 terms used in dc characteristics parameter symbol meaning off-state output leakage current i oz indicates the current that flows from the power supply pins when the rated power supply voltage is applied when a 3-state output has high impedance. output short circuit current i os indicates the current that flows when the output pin is shorted (to gnd pins) when output is at high-level. input leakage current i i indicates the current that flows when the input voltage is supplied to the input pin. low-level output current i ol indicates the current that flows to the output pins when the rated low-level output voltage is being applied. high-level output current i oh indicates the current that flows from the output pins when the rated high-level output voltage is being applied. 3.3 electrical specifications absolute maximum ratings parameter symbol condition rating unit power supply voltage v dd33 v dd25 3.3 v power supply rail 2.5 v power supply rail ? 0.5 to + 4.6 ? 0.5 to + 3.6 v v input voltage, 5 v buffer v i 3.0 v v dd33 3.6 v v i < v dd33 + 3.0 v ? 0.5 to + 6.6 v input voltage, 3.3 v buffer v i 3.0 v v dd33 3.6 v v i < v dd33 + 1.0 v ? 0.5 to + 4.6 v input voltage, 2.5 v buffer v i 2.3 v v dd25 2.7 v v i < v dd25 + 0.9 v ? 0.5 to + 3.6 v output voltage, 5 v buffer v o 3.0 v v dd33 3.6 v v o < v dd33 + 3.0 v ? 0.5 to + 6.6 v output voltage, 3.3 v buffer v o 3.0 v v dd33 3.6 v v o < v dd33 + 1.0 v ? 0.5 to + 4.6 v output voltage, 2.5 v buffer v o 2.3 v v dd25 2.7 v v o < v dd25 + 0.9 v ? 0.5 to + 3.6 v output current, 5 v buffer i o i ol = 6 ma 20 ma output current, 3.3 v buffer i o i ol = 6 ma i ol = 3 ma 20 10 ma ma operating ambient temperature t a 0 to + 70 c storage temperature t stg ? 65 to + 150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameters. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. the ratings and conditions indicated for dc char acteristics and ac characteristics represent the quality assurance range during normal operation.
preliminary data sheet s17100ej2v0ds 16 pd720133 two power supply rails limitation the pd720133 has two power supply rails (2.5 v, 3.3 v). the system will require the power supply rail to be stable at v dd level by a specified time. however, there are difference between the time of v dd25 and v dd33 becoming stable. the pd720133 requires that v dd25 becomes stable before v dd33 . also, it is necessary that v dd33 be powered within 100 ms after v dd25 became stable. in any case, t he system must ensure that the absolute maximum ratings for v i / v o are not exceeded. system reset signaling must be asserted after the specified time of which both v dd25 and v dd33 become stable.
preliminary data sheet s17100ej2v0ds 17 pd720133 recommended operating ranges parameter symbol condition min. typ. max. unit operating voltage v dd33 3.3 v for v dd33 pins 3.0 3.3 3.6 v v dd25 2.5 v for v dd25 pins 2.3 2.5 2.7 v v dd25 2.5 v for av dd25 pins 2.3 2.5 2.7 v high-level input voltage v ih 5.0 v high-level input voltage 2.0 5.5 v 3.3 v high-level input voltage 2.0 v dd33 v 2.5 v high-level input voltage 1.7 v dd25 v low-level input voltage v il 5.0 v low-level input voltage 0 0.8 v 3.3 v low-level input voltage 0 0.8 v 2.5 v low-level input voltage 0 0.7 v hysteresis voltage v h 5 v hysteresis voltage 0.3 1.5 v 3.3 v hysteresis voltage 0.2 1.0 v input rise time t ri normal buffer 0 200 ns schmitt buffer 0 10 ms input fall time t fi normal buffer 0 200 ns schmitt buffer 0 10 ms
preliminary data sheet s17100ej2v0ds 18 pd720133 dc characteristics (v dd33 = 3.0 to 3.6 v, v dd25 = 2.3 to 2.7 v, t a = 0 to + 70 c) control pin block parameter symbol condition min. max. unit off-state output current i oz v o = v dd33, v dd25 or v ss 10 a output short circuit current i os note ? 250 ma low-level output current 5.0 v low-level output current 3.3 v low-level output current 3.3 v low-level output current i ol v ol = 0.4 v v ol = 0.4 v v ol = 0.4 v 6.0 6.0 3.0 ma ma ma high-level output current 5.0 v high-level output current 3.3 v high-level output current 3.3 v high-level output current i oh v oh = 2.4 v v oh = 2.4 v v oh = 2.4 v ? 2.0 ? 6.0 ? 3.0 ma ma ma input leakage current 3.3 v buffer 5.0 v buffer i i v i = v dd or v ss v i = v dd or v ss 10 10 a a note it is specified under the assumption that only one pin on the lsi is sh ort-circuited for not more than one second.
preliminary data sheet s17100ej2v0ds 19 pd720133 usb interface block parameter symbol conditions min. max. unit serial resistor between dp (dm) and rsdp (rsdm) r s 38.61 39.39 ? output pin impedance z hsdrv includes r s resistor 40.5 49.5 ? bus pull-up resistor on upstream facing port r pu 1.5 k ? 5% consists of resistance of transistor and pull-up resistor 1.485 1.515 ? termination voltage for upstream facing port pull-up v term 3.0 3.6 v input levels for full-speed: high-level input voltage (drive) v ih 2.0 v high-level input voltage (floating) v ihz 2.7 3.6 low-level input voltage v il 0.8 v differential input sensitivity v di ? (d+) ? (d ? ) ? 0.2 v differential common mode range v cm includes v di range 0.8 2.5 v output levels for full-speed: high-level output voltage v oh r l of 14.25 k ? to v ss 2.8 3.6 v low-level output voltage v ol r l of 1.425 k ? to 3.6 v 0.0 0.3 v se1 v ose1 0.8 v output signal crossover point voltage v crs 1.3 2.0 v input levels for high-speed: high-speed squelch det ection threshold (differential signal) v hssq 100 150 mv high-speed disconnect det ection threshold (differential signal) v hsdsc 525 625 mv high-speed data signaling common mode voltage range v hscm ? 50 + 500 mv high-speed differential input signaling level see figure 3-4 . output levels for high-speed: high-speed idle state v hsoi ? 10.0 + 10.0 mv high-speed data signaling high v hsoh 360 440 mv high-speed data signaling low v hsol ? 10.0 + 10.0 mv chirp j level (differential signal) v chirpj 700 1100 mv chirp k level (differential signal) v chirpk ? 900 ? 500 mv
preliminary data sheet s17100ej2v0ds 20 pd720133 figure 3-1. differential input sensitivity range for low-/full-speed 4.6 ? 1.0 input voltage range (v) differential input voltage range differential output crossover voltage range 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 figure 3-2. full-speed buffer v oh /i oh characteristics for high-speed capable transceiver max. min. ? 80 ? 60 ? 40 ? 20 0 v dd ? 0.3 v out (v) i out (ma) v dd ? 2.3 v dd ? 3.3 v dd ? 0.8 v dd v dd ? 1.3 v dd ? 1.8 v dd ? 2.8 figure 3-3. full-speed buffer v ol /i ol characteristics for high-speed capable transceiver max. min. 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 v out (v) i out (ma)
preliminary data sheet s17100ej2v0ds 21 pd720133 figure 3-4. receiver sensitivity for transceiver at dp/dm 0 v differential + 400 mv differential ? 400 mv differential unit interval level 1 level 2 0% 100% point 5 point 2 point 1 point 3 point 4 point 6 figure 3-5. receiver measurement fixtures vbus d+ d- gnd 15.8 ? + to 50 ? inputs of a high speed differential oscilloscope, or 50 ? outputs of a high speed differential data generator ? 50 ? coax 50 ? coax usb connector nearest device test supply voltage 15.8 ? 143 ? 143 ? pin capacitance parameter symbol condition min. max. unit input capacitance c in 4 6 pf output capacitance c out 4 6 pf i/o capacitance c io v dd = 0 v, t a = 25c f c = 1 mhz unmeasured pins returned to 0 v 4 6 pf
preliminary data sheet s17100ej2v0ds 22 pd720133 power consumption (1) the power consumption when device works as bus-powered mode symbol condition max. unit v dd25 v dd33 av dd25 the power consumption dur ing device unconfigured stage p enum-bus high-speed operating full-speed operating 55 25 3 4 10 10 ma ma the power consumption during device configured stage p w-bus high-speed operating full-speed operating 100 75 22 13 10 10 ma ma p w_spd-bus the power consumption under suspend state 15 235 5 a (2) the power consumption when device works as self-powered mode symbol condition max. unit v dd25 v dd33 av dd25 the power consumption dur ing device unconfigured stage p enum-self high-speed operating full-speed operating 90 60 5 5 10 10 ma ma the power consumption dur ing device configured stage p w-self high-speed operating full-speed operating 100 75 25 13 10 10 ma ma p w_spd-self the power consumption under suspend state 50 500 15 a p w_unp the power consumption under unplug state 50 500 15 a p w_com the power consumption under combo mode the device is releasing the ide bus. 50 500 15 a
preliminary data sheet s17100ej2v0ds 23 pd720133 ac characteristics (v dd33 = 3.0 to 3.6 v, v dd25 = 2.3 to 2.7 v, t a = 0 to + 70 c) system clock ratings parameter symbol condition min. typ. max. unit x?tal ? 500 ppm 30 + 500 ppm mhz clock frequency f clk oscillator block ? 500 ppm 30 + 500 ppm mhz clock duty cycle t duty 45 50 55 % remarks 1. recommended accuracy of clock frequency is 100 ppm. 2. required accuracy of x?tal or oscillator block is including initial frequency accuracy, the spread of x?tal capacitor loading, supply voltage, temperature, and aging, etc. system reset signaling parameter symbol conditions min. max. unit reset active time t rst 2 s usb interface block (1/2) parameter symbol conditions min. max. unit full-speed source electrical characteristics rise time (10% - 90%) t fr c l = 50 pf, r s = 36 ? 4 20 ns fall time (90% - 10%) t ff c l = 50 pf, r s = 36 ? 4 20 ns differential rise and fall time matching t frfm (t fr /t ff ) 90 111.11 % full-speed data rate for device which are high-speed capable t fdraths average bit rate 11.9940 12.0060 mbps frame interval t frame 0.9995 1.0005 ms consecutive frame interval jitter t rfi no clock adjustment 42 ns source jitter total (including frequency tolerance): to next transition for paired transitions t dj1 t dj2 ? 3.5 ? 4.0 + 3.5 + 4.0 ns ns source jitter for differential transition to se0 transition t fdeop ? 2 + 5 ns receiver jitter: to next transition for paired transitions t jr1 t jr2 ? 18.5 ? 9 + 18.5 + 9 ns ns source se0 interval of eop t feopt 160 175 ns receiver se0 interval of eop t feopr 82 ns width of se0 interval during differential transition t fst 14 ns
preliminary data sheet s17100ej2v0ds 24 pd720133 (2/2) parameter symbol conditions min. max. unit high-speed source electrical characteristics rise time (10% - 90%) t hsr 500 ps fall time (90% - 10%) t hsf 500 ps driver waveform see figure 3-6 . high-speed data rate t hsdrat 479.760 480.240 mbps microframe interval t hsfram 124.9375 125.0625 s consecutive microframe interval difference t hsrfi 4 high-speed bit times data source jitter see figure 3-6 . receiver jitter tolerance see figure 3-4 . device event timings time from internal power good to device pulling d+ beyond v ihz (min.) (signaling attached) t sigatt 100 ms debounce interval provided by usb system software after attach t attdb 100 ms inter-packet delay for full-speed t ipd 2 bit times inter-packet delay for device response w/detachable cable for full-speed t rspipd1 6.5 bit times high-speed detection start time from suspend t sca 2.5 s sample time for suspend vs reset t csr 100 875 s time to detect bus suspend state t spd 3.000 3.125 ms power down under suspend t sus 10 ms reversion time from suspend to high-speed t rhs 1.333 s drive chirp k width t cko 1 ms finish chirp k assertion t fca 7 ms start sequencing chirp k-j-k-j-k-j t ssc 100 s finish sequencing chirp k-j t fsc ? 500 ? 100 s detect sequencing chirp k-j width t csi 2.5 s sample time for sequencing chirp t scs 1 2.5 ms reversion time to high-speed t rha 500 s high-speed detection start time t hds 2.5 3000 s reset completed time t drs 10 ms
preliminary data sheet s17100ej2v0ds 25 pd720133 ide interface block pio mode parameter symbol mode 0 mode 1 mode 2 mode 3 mode 4 unit cycle time (min.) t 0 600 383 240 180 120 ns address setup time (min.) t 1 70 50 30 30 25 ns 16 bits dior/diow pulse width (min.) t 2 165 125 100 80 70 ns 8 bits dior/diow pulse width (min.) 290 290 290 80 70 ns dior/diow recovery time (min.) t 2i ? ? ? 70 25 ns diow data setup time (min.) t 3 60 45 30 30 20 ns diow data hold time (min.) t 4 30 20 15 10 10 ns dior data setup time (min.) t 5 50 35 20 20 20 ns dior data hold time (min.) t 6 5 5 5 5 5 ns dior 3-state delay time (max.) t 6z 30 30 30 30 30 ns address hold time (min.) t 9 20 15 10 10 10 ns iordy read data valid time (min.) note t rd 0 0 0 0 0 ns iordy setup time (min.) note t a 35 35 35 35 35 ns iordy pulse width (max.) note t b 1250 1250 1250 1250 1250 ns iordy inactive to hi-z time (max.) note t c 5 5 5 5 5 ns note iordy is an option in mode 0 - 2. iordy is essential in modes 3 and 4. multi word dma mode parameter symbol mode 0 mode 1 mode 2 unit cycle time (min.) t 0 480 150 120 ns dior/diow pulse width (min.) t d 215 80 70 ns dior data access time (max.) t e 150 60 50 ns dior data hold time (min.) t f 5 5 5 ns dior data setup time (min.) t gr 100 30 20 ns diow data setup time (min.) t gw 100 30 20 ns diow data hold time (min.) t h 20 15 10 ns dmack setup time (min.) t i 0 0 0 ns dmack hold time (min.) t j 20 5 5 ns dior negate pulse width (min.) t kr 50 50 25 ns diow negate pulse width (min.) t kw 215 50 25 ns dior-dmarq delay time (max.) t lr 120 40 35 ns diow-dmarq delay time (max.) t lw 40 40 35 ns dmack 3-state delay time (max.) t z 20 25 25 ns cs setup time (min.) t m 50 30 25 ns cs hold time (min.) t n 15 10 10 ns
preliminary data sheet s17100ej2v0ds 26 pd720133 ultra dma mode mode 0 mode 1 mode 2 mode 3 mode 4 parameter symbol min. max. min. max. min. max. min. max. min. max. unit average cycle time for 2 cycles t 2cyc 240 - 160 - 120 - 90 - 60 - ns minimum cycle time for 2 cycles t 2cyc 235 - 156 - 117 - 86 - 57 - ns cycle time for 1 cycle t cyc 114 - 75 - 55 - 39 - 25 - ns data setup time on receive side t ds 15 - 10 - 7 - 7 - 5 - ns data hold time on receive side t dh 5 - 5 - 5 - 5 - 5 - ns data setup time on transmit side t dvs 70 - 48 - 34 - 20 - 6 - ns data hold time on transmit side t dvh 6 - 6 - 6 - 6 - 6 - ns first strobe time t fs 0 230 0 200 0 170 0 130 0 120 ns interlock time with limitation t li 0 150 0 150 0 150 0 100 0 100 ns minimum interlock time t mli 20 - 20 - 20 - 20 - 20 - ns interlock time without limitation t ui 0 - 0 - 0 - 0 - 0 - ns output release time t az - 10 - 10 - 10 - 10 - 10 ns output delay time t zah 20 - 20 - 20 - 20 - 20 - ns output stabilization time (from release) t zad 0 - 0 - 0 - 0 - 0 - ns envelope time t env 20 70 20 70 20 70 20 55 20 55 ns strobe dmardy delay time t sr - 50 - 30 - 20 - na - na ns last strobe time t rfs - 75 - 60 - 50 - 60 - 60 ns pause time t rp 160 - 125 - 100 - 100 - 100 - ns iordy pull-up time t ioryz - 20 - 20 - 20 - 20 - 20 ns iordy wait time t ziory 0 - 0 - 0 - 0 - 0 - ns dmack setup/hold time t ack 20 - 20 - 20 - 20 - 20 - ns strobe stop time t ss 50 - 50 - 50 - 50 - 50 - ns
preliminary data sheet s17100ej2v0ds 27 pd720133 serial rom interface block parameter symbol conditions min. max. unit clock frequency t scl 100 khz clock pulse width low t low 4.7 s clock pulse width high t high 4.0 s clock low to data valid t aa 100 4500 ns start hold time t hd.sta 4.0 s start setup time t su.sta 4.7 s data in hold time t hd.dat 0 ns data in setup time t su.dat 0.2 s data out hold time t dh 50 ns stop setup time t su.sto 4.7 s time the bus must be free before a new transmission can start t buf 10 s write cycle time t wr 10 ms
preliminary data sheet s17100ej2v0ds 28 pd720133 figure 3-6. transmit waveform for transceiver at dp/dm 0 v differential + 400 mv differential ? 400 mv differential unit interval level 1 level 2 0% 100% point 4 point 3 point 1 point 2 point 5 point 6 figure 3 - 7. transmitter measurement fixtures vbus d+ d- gnd 15.8 ? + to 50 ? inputs of a high speed differential oscilloscope, or 50 ? outputs of a high speed differential data generator ? 50 ? coax 50 ? coax usb connector nearest device test supply voltage 15.8 ? 143 ? 143 ?
preliminary data sheet s17100ej2v0ds 29 pd720133 timing diagram system reset timing resetb t rst remark after chip reset, this chip reads the serial rom firs t. do not reset while the serial rom is read. the read operation is completed in the period, which is calculated with the following expression. 5 + 0.1197 bytes (serial rom size) + 0.5678 (ms) example in the case of 512 bytes: 66.855 ms , in the case of 8 kbytes: 986.15 ms usb power-on and connection events t sigatt d + or d ? hub port power ok attatch detected reset recovery time usb system software reads device speed 4.01 v v bus v ih(min) v ih hub port power-on 10 ms t attdb usb differential data jitter for full-speed t period differential data lines crossover points consecutive transitions n t period + t dj1 paired transitions n t period + t dj2
preliminary data sheet s17100ej2v0ds 30 pd720133 usb differential-to-eop transition skew and eop width for full-speed t period differential data lines crossover point crossover point extended source eop width: t feopt receiver eop width: t feopr diff. data-to- se0 skew n t period + t fdeop usb receiver jitter tolerance for full-speed differential data lines t period t jr t jr1 t jr2 consecutive transitions n t period + t jr1 paired transitions n t period + t jr2 usb connection sequence on full-speed system bus t hds t sca t cko t scs t fca t drs chirp k device out reversion to full-speed mode fsj fsj pull-up is active. t 0 usb bus
preliminary data sheet s17100ej2v0ds 31 pd720133 usb connection sequence on high-speed system bus t hds t sca t cko t scs t fca chirp k device out reset complete fsj pull-up is active. t 0 usb bus t ssc t csi t rha t fsc chirp state from host/hub reversion to high-speed mode kkjjkj k j usb reset sequence from suspend state on full-speed system bus t sca t cko t scs t fca t drs chirp k device out fsj fsj pull-up is active. t 0 usb bus usb reset sequence from suspend state on high-speed system bus t sca t cko t scs t fca chirp k device out reversion to high-speed mode fsj pull-up is active. t 0 usb bus t ssc t csi t rha t fsc chrip state from host/hub reset complete kkjkkj j j usb suspend and resume on full-speed system bus usb bus fsj fsj fsk fs eop t sus power will be down note time required to relock pll and stabilize oscillator. t spd
preliminary data sheet s17100ej2v0ds 32 pd720133 usb suspend and resume on high-speed system bus usb bus fsj fsk high-speed packet t spd t t sus power will be down note time required to relock pll and stabilize oscillator. t csr reversion to full-speed mode t rhs high-speed packet reversion to high-speed mode t 0 ide pio mode timing t 1 idecs1b, idecs0b ideea2-ideea0 ideiorb ideiowb ided15-ided0 ided15-ided0 ideiordy h l h l h l h l h l t 0 t 2 t 4 t 2i t 5 t 6 t 6z t 3 t a t 9 t c t rd t b (write) (read) ide multi word dma mode timing t 0 h l h l h l h l h l idedrq idedakb ideiorb ideiowb ided15-ided0 (read) ided15-ided0 (write) h l t kr /t kw t m t z t d t e t f t gr t h t i t j t gw t lr /t lw t n idecs1b, idecs0b
preliminary data sheet s17100ej2v0ds 33 pd720133 ide ultra dma mode data-in timing t ack crc t 2cyc t cyc t dvs t dvh t fs t cyc t az t ziory t ack t ioryz t ss t li t mli t ui t zad t zah t env t li t li t az t dvh t dvs t zad t fs t env t ack t ack t ack t ack t ack t ack h l h l h l h l h l h l idedrq idedakb ided15-ided0 h l ideiowb (stop) ideiordy (hdmardy) ideiorb (dstrobe) idea2-idea0 h l idecs1b, idecs0b data data data ide ultra dma mode data-in stop timing t sr t rp t rfs h l h l h l h l h l h l idedrq idedakb ided15-ided0 ideiowb (stop) ideiorb (hdmardy) ideiordy (dstrobe) ide ultra dma mode data-in end timing crc t rps t ioryz t rp t li t mli t zah t dvh t dvs t ack t az t ack t li t mli t ack h l h l h l h l h l h l idedrq idedakb ided15-ided0 h l ideiowb (stop) ideiorb (hdmardy) ideiordy (dstrobe) idecs1b, idecs0b idea2-idea0
preliminary data sheet s17100ej2v0ds 34 pd720133 ide ultra dma mode data-out timing t rfs t rp t ack t ui t ack t ack t ack t ack t ack t li t env t ui t li t mli t ack t ack t ziory t dvs t dvh t 2cyc t cyc t cyc t dvs t dvh t ioryz t mli t li h l h l h l h l h l h l idedrq idedakb ided15-ided0 h l ideiowb (stop) ideiordy (ddmardy) ideiorb (hstrobe) idea2-idea0 h l idecs1b, idecs0b data data data crc ide ultra dma mode data-out stop timing t sr t rp t rfs h l h l h l h l h l h l idedrq idedakb ided15-ided0 ideiowb (stop) ideiorb (hdmardy) ideiordy (dstrobe) ide ultra dma mode data-out end timing h l h l h l h l h l h l idedrq idedakb ided15-ided0 h l crc t ioryz t ss t li t mli t dvh t dvs t ack ideiowb (stop) ideiorb (hdmardy) ideiordy (dstrobe) idecs1b, idecs0b idea2-idea0 t li t ack t ack t li
preliminary data sheet s17100ej2v0ds 35 pd720133 ide ultra dma mode data skew timing xstrobe dd0 : : dd15 t 2cyc t cyc t dvs t dvh data data data t ds t dh ideiorb (output side) ided15-ided0 (output side) output side input side delay, skew, etc., by cable ideiordy (input side) ided15-ided0 (input side) h l h l h l h l t cyc serial rom access timing scl sda (output) sda (input) t su.sta t hd.sta t su.dat t high t low t low t hd.dat t aa t dh t su.sto t buf serial rom write cycle timing pio1 pio0 word n 8th bit ack stop condition start condition t wr
preliminary data sheet s17100ej2v0ds 36 pd720133 4. package drawing ? pd720133gb-yeu-a ? pd720133gb-yeu-y m 48 32 33 64 1 17 16 49 s n s 64-pin plastic tqfp (fine pitch) (10x10) item millimeters a b d g h 12.0 0.2 10.0 0.2 0.5 (t.p.) 0.22 0.05 1.25 j 12.0 0.2 k c 10.0 0.2 i 0.08 1.0 0.2 l 0.5 0.08 n p 1.0 q 0.1 0.05 f 1.25 s t 1.10 0.10 0.25 s64gb-50-yeu-1 u 0.6 0.15 r3 + 4 ? 3 m 0.17 + 0.03 ? 0.07 note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. j c d a b k m p detail of lead end s l u q r t g f hi
preliminary data sheet s17100ej2v0ds 37 pd720133 5. recommended soldering conditions the pd720133 should be soldered and mounted un der the following recommended conditions. for soldering methods and conditions other than those recommended below, please contact your nec electronics sales representative. for technical information, please refer to the following website. semiconductor device mount manual (http ://www.necel.com/pkg/en/mount/index.html) pd720133gb-yeu-a / pd720133gb-yeu-y: 64-pin plastic tqfp (fine pitch) (10 10) soldering method soldering conditions symbol infrared reflow package peak temperature time at peak temperature time at 220c or higher preheat time (160 to 180c) maximum count exposure limit : 260c : within 10 seconds : within 60 seconds : 60 to 120 seconds : 3 times or less : 3 days note (after that, prebake at 125c for 10 hours) ir60-103-3 partial heating pin temperature: 300c max., time: 3 seconds or less (per pin row) ? note after opening the dry pack, store it at 25c or le ss and 65% rh or less for the allowable storage period.
preliminary data sheet s17100ej2v0ds 38 pd720133 [memo]
preliminary data sheet s17100ej2v0ds 39 pd720133 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. notes for cmos devices
pd720133 eeprom is a trademark of nec electronics corporation. the information in this document is current as of june, 2004. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ?

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